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But how do you know, that if kroah.com would use Let's Encrypt it would belong to Greg K-H? What if his true WEB-site would be e.g. greg-k-h.com?

Right. Also, when it comes to the other aspects of TLS, such as preventing middlemen from making sense of what information flows between you and the server, what exactly is the threat in this case? I mean, it's a public blog post, which you only ask to read and so you are served.

It's not about threat, it's about privacy. I understand your statements but 'what is the threat in this case' to answer that: I don't want to know, I've moved on from those worries. Always encrypt.

What privacy? Whoever is watching your traffic can see you accessed their website with HTTPS, they can guess with high accuracy which article you are reading based on the response size.

Any hops along the paths and whatever they split off to by whoever. And of course they can, even with HTTPS the Client Hello is unencrypted.

Unencrypted data transmission just isn't a thing I'm interested in with it being 2025.


ASML cannot be avoided for 7nm and better due to EUV.

Generally there is a hidden starvation (I'm not sure the exact term), when one consumes just enough calories to survive a bit longer but almost no vitamins and minerals to live normal life.

Similar to polluted air/environment such deaths will hardly be backtracked to the true roots.

The most recent were deaths in conjunction with COVID. Was it due to COVID directly, indirectly or it was so bad that COVID could not really make it worse...


> Before P2996, generating Python bindings required either:

I'm missing nanobind here.

> Method lookup. Python sees a.dot and searches for the dot attribute. It checks a.__dict__,

> Each attribute access (self.x) involves:

    Dictionary lookup in self.__dict__
Since C++ classes are fixed, I'd expect attributes to be declared once in python (slots).

One thing yet important for cross-language projects: callbacks (events). Would be nice if the sample could be extended.


Thanks for the suggestion, let me take a good look at callbacks.

Another thing that I can't make work elegantly is compiling template functions from C++, since we have no clue to guess which types will be instantiated in the Python code (and they can even depend on user input, so only determined at runtime)


> KLEVV

Just looked at standard desktop: still no 64GB 5600MT/s modules. CUDIMMs are missing 32GB.

> And don't forget about Nanya

BTW, what is the status of Elpida now?


Elpida was purchased by Micron after the financial crisis (they bought it out of bankdruptcy for a swan song in 2013). Much of the Micron DRAM you might buy is made at the former Elipida fab in Hiroshima.

Mostly R&D.

Using digital chips instead of some novel analog approach is even greater waste.

> China's AI Analog Chip Claimed to Be 3000X Faster Than Nvidia's A100 GPU (04.11.2023)

https://news.ycombinator.com/item?id=38144619

> Q.ANT’s photonic chips – which compute using light instead of electricity – promise to deliver a 30-fold increase in energy efficiency and a 50-fold boost in computing speed, offering transformative potential for AI-driven data centers and HPC environments. (24.02.2025)

https://qant.com/press-releases/q-ant-and-ims-chips-launch-p...


> enterprise-level RAM sticks will operate with 9 8-bit-wide chips

Since DDR5 has 2 independent subchannels, 2 additional chips are needed.


> What we need is automated theorem discovery.

I've been thinking mathematicians have fun doing math, making discoveries, crafting proofs.

Does Tour de France & Co. make no sense since small, lightweight and powerful e-bicycles appeared?

Using computer as a helper like bicycles is one thing, using LLMs seems more like e-bicycle and is something another.


> DDR4 is EOL

11 years after specification released.

DDR4 makes it possible since 5 and half years to build 128GB AMD PC using 4x 32GB DDR4-3200 1.2V JEDEC modules. Only since half a year it is at last possible to build AMD PC with 128GB DDR5-5600 RAM. Because Ryzen DDR5 controller cannot operate with 2 sticks sharing the same channel at JEDEC speed/voltage.

DDR4 just cannot be EOL already because of unbuffered ECC! Even today it is not possible to have 128GB with 2 DDR5 sticks on AMD. Only 96GB.

And actually I'd expect 256GB (DDR5-8800 1.1V JEDEC) to be possible with DDR5. We're now only from 4000 to 5600 5(!) years since the specification was published. What if AMD achieves this only few months before DDR5 EOL?..

> DDR6 will be out in 2026 with consumer availability in 2027

... or not at all?..


Now that PCIe 5.0 SSDs are available since 6+ months and you could backup your SSD with 15 GB/s but:

> you’re still writing at 1.5GB/sec.

Except of few seconds at the start, the whole process lasts as if you had PCIe 2.0 (15+ years ago). Having so fast SSDs there is no chance to make a quick backup/restore. And during restore you're second time in a row too slow.

It's crazy that instead of using slow PLC at the time of slow PCIe 1.0, back then fast SLC was in use. Now with PCIe 5.0 when you really need fast SLC, you get slow TLC or very slow QLC or even worse PLC coming.


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