There have been "minimum noninfringing change" MIPS clones, by doing something like leaving out the patented unaligned load and store instructions, but otherwise being identical and compatible with MIPS software and compilers etc.
RISC-V is completely different and incompatible with MIPS at the binary level. The opcodes are all different. The opcode and register fields are build from opposite ends of the word. The conditional branching model is different (MIPS r6 later copied RISC-V's version). The sizes of immediate and offset values is only 12 bits vs 16 in MIPS – which is a major reason for RISC-V having a lot more encoding space free for future instructions. There are of course no branch or load delay slots in RISC-V – something that MIPS again copied in r6.
There is a certain flavour that is similar, but the details are utterly different.
There have been "minimum noninfringing change" MIPS clones, by doing something like leaving out the patented unaligned load and store instructions, but otherwise being identical and compatible with MIPS software and compilers etc.
RISC-V is completely different and incompatible with MIPS at the binary level. The opcodes are all different. The opcode and register fields are build from opposite ends of the word. The conditional branching model is different (MIPS r6 later copied RISC-V's version). The sizes of immediate and offset values is only 12 bits vs 16 in MIPS – which is a major reason for RISC-V having a lot more encoding space free for future instructions. There are of course no branch or load delay slots in RISC-V – something that MIPS again copied in r6.
There is a certain flavour that is similar, but the details are utterly different.